**Operation:**

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Destination / Source -->; Destination

**Compatibility:** MC68020/MC68030/MC68040

**Assembler Syntax:**

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DIVSL.L <ea>, Dr:Dq` `

32/32 -->; 32r:32q

**Attributes:** Size = (Long)

**Description:** Divides the signed destination operand by the

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signed source operand and stores the signed result in the

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destination.

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This instruction divides a long word by a long word. The

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result is a long-word quotient and a long-word remainder.

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Two special condition may arise during the operation:

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1. Division by zero causes a trap.

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2. Overflow may be detected and set before the inst-

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ruction completes. If the instruction detects

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an overflow, it sets the overflow condition

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code and the operands are unaffected.

**Condition Codes:**

\c32220

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X Not affected.

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N Set if the quotient is negative. Cleared otherwise.

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Undefined if overflow or divide by zero occurs.

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Z Set if the quotient is zero. Cleared otherwise.

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Undefined if overflow or divide by zero occurs.

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V Set if the division overflow occurs; undefined if

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divide by zero occurs. Cleared otherwise.

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C Always cleared.

**Instruction Format:**

\i2-+--++---+u6Effective Address,3Mode,3Reg,-3Reg Dq,+--------3Reg Dr,

**Instruction Fields:**

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Effective Address field -- Specifies the source operand.

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Only data addresssing modes are allowed as shown:

\mBFF

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Register Dq field -- Specifies a data register for the dest-

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ination operand. The low-order 32 bits of the

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dividend comes from this register, and the 32-

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bit quotient is loaded into this register.

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Register Dr field -- After the division, this register contains

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the 32-bit remainder. If Dr and Dq are the same

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register, only the quotient is returned.

Note: Overflow occurs if the quotient is larger than a 32-bit

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signed integer. The assembler accepts TDIVS as an

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alternative syntax for the DIVSL instruction.